This invention relates to a lead frame for a semiconductor device and also to a method of producing such a lead frame.
FIG. 3 is a plan view showing ordinary-type semiconductor device lead frames for mounting a semiconductor device, such as a transistor and an IC, thereon, and FIG. 4 is a view showing a condition in which the semiconductor device is mounted on the lead frame. In FIGS. 3 and 4, reference numeral 4 denotes a pad portion, reference numeral 5 an inner lead portion, reference numeral 6 an outer lead portion, reference numeral 7 a tie-bar portion, reference numeral 8 a semiconductor chip (semiconductor device), reference numeral 9 an adhesive, reference numeral 10 an electrode pad, reference numeral 11 a wire, and reference numeral 12 a sealing resin.
The design and characteristics of the semiconductor device lead frame of the above construction will now be described.
In FIG. 3, the plurality of inner lead portions 5 are provided around the pad portion 4 (for mounting the semiconductor chip 8 thereon) in spaced relation thereto, and the inner lead portions 5 are connected respectively to the outer lead portions 6 through the tie-bar portion 7. The semiconductor device lead frame, having a configuration as shown in FIG. 3, can be obtained by pressing or etching a plate-like stock made of Cu alloy or Fexe2x80x94Ni alloy. In order to prevent the oxidation of the pad portion 4 and the inner lead portions 5, these portions are partially plated with precious metal, such as Ag, to have a plating film with a thickness of 3 to 5 xcexcm.
Generally, the semiconductor chip 8 is mounted on such a semiconductor device lead frame, using the following process. As shown in FIG. 4, the semiconductor chip 8 is die-bonded to the pad portion 4 by the adhesive 9, and the electrode pads 10, formed beforehand on the semiconductor chip 8, are wire-bonded to the respective inner lead portions 5 by the wires 11 made of Au, Al or Cu, thus creating an electrical connection therebetween.
Thereafter, a predetermined portion of the lead frame, including the wire-bonded portions, is sealed by the sealing resin 12 such as an epoxy resin. Then, solder, such as Snxe2x80x94Pb alloy, is plated onto the outer lead portions 6, thereby imparting solderability thereto, and the tie-bar portions 7 are cut off, and then a deburring process is effected, and then the outer lead portions 6 are bent, hereby completing the resin-sealed semiconductor device. The resin-sealed semiconductor device thus produced is mounted on a board (such as a printed circuit board) of an external equipment, and the relevant wiring on this board is connected by soldering to the outer lead portions 6, thereby forming an intended electronic equipment circuit.
Incidentally, the plating treatment for the outer lead portions 6 is usually effected using a hot dipping method or an electroplating method. However, in the hot dipping method, the high-temperature (230 to 400xc2x0 C.) treatment is effected, and therefore the resin-sealed semiconductor device undergoes a high thermal stress, so that fine gaps are sometimes caused between the sealing resin 12 and the lead frame, thereby lowering the reliability of the resin-sealed semiconductor device. In the case of the electroplating method, a plating solution is usually acid or alkali, and therefore part of the sealing resin 12 is sometimes corroded, so that the plating solution intrudes into the sealing resin 12, and as a result the wires 11 and the electrode pads 10 are subjected to corrosion, thereby lowering the reliability of the resin-sealed semiconductor device.
In view of the fact that the reliability of the resin-sealed semiconductor device is thus lowered, there has recently been used a solder PPF (Pre-Plated Frame) method in which solder, such as Snxe2x80x94Pb alloy, is applied beforehand onto the outer lead portions 6, and thereafter the semiconductor chip is mounted on the lead frame. However, when this solder PPF method is used, it is necessary to effect the wire bonding operation (which is the later step) at sufficiently low temperatures so that the Snxe2x80x94Pb alloy will not be melted by heat produced during this wire bonding operation. And besides, where the plate-like stock is a Cu material, the thermal diffusion of ions of impurities, contained in this Cu material, into the Snxe2x80x94Pb alloy lowers the solderability of the outer lead portions 6, and therefore this must be taken into consideration.
Therefore, recently, there have been proposed a lead frame (see Japanese Patent Examined Publication No. 63-49382 and Japanese Patent Unexamined Publication No. 63-2358) in which a Pd coating or a Pd alloy coating is formed on the pad portion 4, the inner lead portions 5 and the outer lead portions 6, a corrosion-resistant lead frame (see Japanese Patent Unexamined Publication No. 2-42753) in which an intermediate layer is formed between a Pd coating and a plate-like stock, thereby reducing the galvanic migration, a lead frame (see Japanese Patent Unexamined Publication No. 4-115558) in which a thin plating film of Au or Ag is formed on a coating of Pd or Pd alloy, thereby enhancing the solder wettability, a lead frame (see Japanese Patent Unexamined Publication No. 5-117898) in which a primary coat, composed, for example, of Ni, Zn or Sn, is formed between a coating of precious metal (e.g. Pd) and a plate-like stock, thereby preventing cracks from developing during a bending operation, and a lead frame (see Japanese Patent Unexamined Publication No. 7-169901) in which a Ni layer, a Pd layer and an Au layer are sequentially formed in a laminated manner on a plate-like stock, and this Pd layer has a multi-layer construction.
A Pd coating, or a Pd alloy coating is a precious metal like Ag and Au, and therefore is chemically stable, and is less liable to oxidize, and is hardly affected by the thermal diffusion from the lead frame body. Therefore, the Pd coating or the Pd alloy coating achieves the good bonding of the semiconductor chip 8 and the good wire bonding properties solder wettability the and of the outer lead portions 6 is good. Furthermore, since the Pd coating or the Pd alloy coating is formed on the lead frame over the entire surface thereof, advantages that are achieved include that the process can be simplified and that the quality of the products is stable.
However, the above conventional semiconductor device lead frames have the following problems.
Recently, the requirements for the characteristics of semiconductor devices have become more severe year after year, and although the Pd coating or the Pd alloy coating is chemically stable, and has the wire bonding properties of an almost acceptable level as described above, it sometimes fails to fully satisfy these stringent requirements. For example, although particular problem is not encountered with the bonding of the semiconductor chip 8 and the wire bonding properties, the Pd coating or the Pd alloy coating on the outer lead portions 6 is oxidized by a high-temperature thermal stress, occurring during the bonding of the semiconductor chip 8, though this coating is precious metal, and as a result the solder wettability at the later step is lowered, thus affecting the solderability. Specifically, it becomes difficult to cover the required solder-wetting area, and the wetting rate decreases, and therefore the time of dipping in a soldering bath increases, thus lowering the efficiency of the operation, and in the worse case, there have been instances in which the solder wetting has not taken place at all. Particularly, with a high-density design of recent semiconductor devices, the space between the adjacent outer lead portions 6 becomes narrower, and at the time of the reflow bonding by cream solder during the mounting of the semiconductor device on the board, the cream solder flows along the surface of the board because of the poor solder wettability, which results in a problem that bridges are caused between the wires, so that the circuit is short-circuited. Although the occurrence of such bridges can be reduced to a certain degree by reducing the amount of coating of the cream solder, this invites another problem. Namely, as a result of the reduced amount of coating of the cream solder, the height of coating of the cream solder is reduced, and in some cases, the outer lead portions 6 cannot be bonded to the board of the external equipment at all because of variations in the gap between the outer lead portions 6 and the board, which results in the problem of the circuit of the electronic equipment being kept open.
In this semiconductor device lead frame and the method of producing this lead frame, it is required to prevent the solder wettability of the Pd coating or the Pd alloy coating, formed on the plate-like stock, from being lowered.
It is an object of this invention to provide a lead frame for a semiconductor device in which the solder wettability of a Pd coating or a Pd alloy coating formed on a sheet-like body is prevented from being lowered.
Another object of the invention to provide a method of producing a lead frame for a semiconductor device in which the solder wettability of a Pd coating or a Pd alloy coating formed on a sheet-like body is prevented from being lowered.
According to one aspect of the present invention, there is provided a lead frame for a semiconductor device in which a Pd coating or a Pd alloy coating is formed on a sheet-like body, and the amount of impurity metal (e.g. Ni) other than Pd or Pd alloy constituents, which impurity metal is contained in the Pd coating or in the Pd alloy coating, is not more than 10 ppm.
With this construction, there is obtained the semiconductor device lead frame in which the solder wettability of the Pd coating or the Pd alloy coating, formed on the sheet-like body, is prevented from being lowered.
According to another aspect of the invention, there is provided a method of producing a lead frame for a semiconductor device in which a Pd coating is formed on a sheet-like body by Pd plating, or a Pd alloy coating is formed on the sheet-like body by Pd alloy plating, and the amount of impurity metal (e.g. Ni) other than Pd or Pd alloy constituents, which impurity metal is contained in a Pd plating solution or in a Pd alloy plating solution, is not more than 10 ppm.